This invention pertains to branch predictions in a computer, and more particularly to branch predictions based on load instructions.
In an effort to improve processor efficiency, computers today engage in branch prediction. Branch prediction involves speculating as to which way a program will go when it reaches a branch point. For example, FIG. 1 shows program 105 with branch instruction 110. At the branch, the program will proceed either with instruction 115-1 or instruction 115-2, depending on whether or not the branch is taken. The processor attempts to determine which path will be followed: i.e., whether instruction 115-1 or instruction 115-2 will follow instruction 110. When successful, branch prediction enables processors, especially pipeline processors (which execute several instructions at different stages at the same time), to execute programs more quickly.
But when a branch prediction fails, any instructions executed by the processor on the wrong path have been wasted. The processor loses any advantage provided by the branch predictor, and needs to execute the instructions along the correct path.
Frequently, the branch taken after a branch instruction correlates well with data recently loaded from memory. For example, in FIG. 1, instruction 120 may be a load instruction, on whose value branch instruction 110 depends. But currently, branch prediction is based on factors such as the path leading to the branch, previous occurrences of the branch, and the values of operands of the branch instruction. Branch prediction, so far, does not correlate with the value of data loaded from memory.
The present invention addresses this and other problems associated with the prior art.